-------------------------------------------------------------------------------
-- mem_signal_mux_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library mem_signal_mux_v1_00_a;
use mem_signal_mux_v1_00_a.all;

entity mem_signal_mux_0_wrapper is
  port (
    A_M : in std_logic_vector(0 to 22);
    A_F : in std_logic_vector(0 to 22);
    DQ_M_I : out std_logic_vector(0 to 15);
    DQ_M_O : in std_logic_vector(0 to 15);
    DQ_M_T : in std_logic_vector(0 to 15);
    DQ_F_I : out std_logic_vector(0 to 15);
    DQ_F_O : in std_logic_vector(0 to 15);
    DQ_F_T : in std_logic_vector(0 to 15);
    OEN_M : in std_logic;
    OEN_F : in std_logic;
    WEN_M : in std_logic;
    WEN_F : in std_logic;
    WEN : out std_logic;
    CEN_M : in std_logic;
    CEN_F : in std_logic;
    A_Out : out std_logic_vector(0 to 22);
    DQ_O : out std_logic_vector(0 to 15);
    DQ_I : in std_logic_vector(0 to 15);
    CEN_M_O : out std_logic;
    CEN_F_O : out std_logic;
    OEN : out std_logic;
    DQ_T : out std_logic_vector(0 to 15)
  );

  attribute x_core_info : STRING;
  attribute x_core_info of mem_signal_mux_0_wrapper : entity is "mem_signal_mux_v1_00_a";

end mem_signal_mux_0_wrapper;

architecture STRUCTURE of mem_signal_mux_0_wrapper is

  component mem_signal_mux is
    port (
      A_M : in std_logic_vector(0 to 22);
      A_F : in std_logic_vector(0 to 22);
      DQ_M_I : out std_logic_vector(0 to 15);
      DQ_M_O : in std_logic_vector(0 to 15);
      DQ_M_T : in std_logic_vector(0 to 15);
      DQ_F_I : out std_logic_vector(0 to 15);
      DQ_F_O : in std_logic_vector(0 to 15);
      DQ_F_T : in std_logic_vector(0 to 15);
      OEN_M : in std_logic;
      OEN_F : in std_logic;
      WEN_M : in std_logic;
      WEN_F : in std_logic;
      WEN : out std_logic;
      CEN_M : in std_logic;
      CEN_F : in std_logic;
      A_Out : out std_logic_vector(0 to 22);
      DQ_O : out std_logic_vector(0 to 15);
      DQ_I : in std_logic_vector(0 to 15);
      CEN_M_O : out std_logic;
      CEN_F_O : out std_logic;
      OEN : out std_logic;
      DQ_T : out std_logic_vector(0 to 15)
    );
  end component;

begin

  mem_signal_mux_0 : mem_signal_mux
    port map (
      A_M => A_M,
      A_F => A_F,
      DQ_M_I => DQ_M_I,
      DQ_M_O => DQ_M_O,
      DQ_M_T => DQ_M_T,
      DQ_F_I => DQ_F_I,
      DQ_F_O => DQ_F_O,
      DQ_F_T => DQ_F_T,
      OEN_M => OEN_M,
      OEN_F => OEN_F,
      WEN_M => WEN_M,
      WEN_F => WEN_F,
      WEN => WEN,
      CEN_M => CEN_M,
      CEN_F => CEN_F,
      A_Out => A_Out,
      DQ_O => DQ_O,
      DQ_I => DQ_I,
      CEN_M_O => CEN_M_O,
      CEN_F_O => CEN_F_O,
      OEN => OEN,
      DQ_T => DQ_T
    );

end architecture STRUCTURE;

